1. Field of the Invention
The present invention relates to a technology for enhancing the yield of EL (Electro Luminescence) display panels and has modes of as an EL display panel, a power supply line drive apparatus, and an electronic device. It should be noted that the EL display panel denotes a self-illuminant display apparatus with EL devices arranged in matrix on a substrate made of glass or other materials.
2. Description of the Related Art
Recently, organic EL panels on which organic EL devices are arranged in matrix have been drawing attention. This is because organic EL panels are excellent in moving picture display characteristics as well as easy in reducing apparatus weight and film thickness.
Currently, two organic EL panel driving schemes are available; passive matrix driving and active matrix driving. Especially, organic EL panels based on the active matrix driving in which an active element (a thin-film transistor) and a hold capacity are arranged for every pixel circuit are under brisk development.
The following shows documents associated with the active matrix driving, for example.
Patent Document 1: Japanese Patent Laid-Open No. 2003-255856
Patent Document 2: Japanese Patent Laid-Open No. 2003-271095
Patent Document 3: Japanese Patent Laid-Open No. 2004-029791
Patent Document 4: Japanese Patent Laid-Open No. 2004-093682
As shown in the above-mentioned Patent Documents, the active matrix driving is of various types. Described in what follows is one of these driving schemes that controls the on state and the off state of each organic EL device by digitally driving one of two power supply lines for supplying a power supply potential to each pixel circuit.
Now, referring to FIG. 1, there is shown an exemplary pixel circuit of the above-mentioned type. A pixel circuit 1 is made up of two N-type thin-film transistors T1 and T2. Of these two transistors, the thin-film transistor T1 is a switching transistor that controls writing of a signal line voltage Vsig to a storage capacity Cs.
On the other hand, the thin-film transistor T2 is a driving transistor that supplies drive current Ids of a magnitude corresponding to a hold voltage Vgs of a storage capacity Cs to an organic EL device D1. The thin-film transistors T1 and T2 are connected to a signal line as follows.
A gate electrode of the thin-film transistor T1 is connected to a scan line SCNL(i) (i being a serial number indicative of row position) that gives a signal line potential write timing. In FIG. 1, a write timing signal is indicated by SCNL(i).
One main electrode of the thin-film transistor T1 is connected to a signal line DL(j) (j being a serial number indicative of a column position) and the other main electrode is connected to a gate electrode of the thin-film transistor T2 and an electrode of the storage capacity Cs.
One main electrode of the thin-film transistor T2 is connected to a drive power supply line DSL(i) (i being a serial number indicative of row position) and the other main electrode is connected to a positive electrode (or an anode electrode) of an organic EL device OLED. In FIG. 1, power supply potential of a high potential (also referred to as a high power supply potential) to be applied to a drive power supply line DSL(i) is indicated by Vcc_H and a power supply potential of low potential (also referred to as a low power supply potential) is indicated by Vcc_L1.
It should be noted that a negative electrode (or a cathode electrode) of the organic EL device OLED is connected to a common power supply line (or a ground line). In FIG. 1, a power supply potential of low potential to be applied to the common power supply line is indicated by Vcc_L2. Meanwhile, the organic EL device OLED is a current-driven element. Therefore, it is desired to flow a current (I*n) obtained by multiplying current I flowing through one pixel circuit by the number of pixels (or n times) to the drive power supply line DSL(i) that is emitting light.
Hence, a wiring resistance of the drive power supply line DSL(i) located on a route along which the power supply potential of high potential is supplied has to be relatively small. If the wiring resistance is large, a voltage drop difference occurs across the drive power supply line DSL(i) to cause problems of a luminance difference depending on the location of scan line and generating heat in the power supply line, for example.
If the number of stages of scan lines making up a valid display area is V, then it is desired to flow current (I*n*V) obtained by multiplying the number of pixels (n times) of current I flowing to one pixel circuit by the number of stages (V times) to a high-potential power supply line that supplies high-potential power supply potential Vcc_H to each drive power supply line DSL(i).
Consequently, it is technically necessary for both the drive power supply line DSL(i) and the high-potential power supply line to be relatively large in wiring width so as to lower the wiring resistance. The following describes these technological requirements with reference to FIGS. 2 and 3. FIG. 2 shows a connection relationship between the pixel circuit 1 and a power supply line drive circuit 3. FIG. 3 shows a wiring pattern of a connected portion between the drive power supply lines DSL and a power supply line drive circuit 7 (or an output stage buffer circuit).
The power supply line drive circuit 3 is made up of a shift register 5 that transfers a power supply line drive pulse to a next scan line for each horizontal scan interval and a buffer circuit 7 (2-stage configuration of input-stage buffer circuit and output-stage buffer circuit).
The two stages of buffer circuits making up the buffer circuit 7 are each configured by a CMOS inverter circuit. In the case of FIG. 2, each p-channel MOS transistor is connected to a high-potential power supply line 11 and each n-channel MOS transistor is connected to a low-potential power supply line 13.
Consequently, if the power supply drive pulse is at H level, high-potential power supply potential Vcc_H is supplied to the drive power supply line DSL(i); if the power supply line drive pulse is at L level, low-potential power supply potential Vcc_L is supplied to the drive power supply line DSL(i).
Meanwhile, if the drive power supply line DSL(i) wide in wiring and the high-potential power supply line 11 are arranged in a crossed manner, a resultant cross area becomes wide. And, this cross appears for every drive power supply line DSL(i). Therefore, let one cross area be S, then a cross area of the entire organic EL panel becomes as large as S*V (V being the number of scan lines or the number of vertical resolutions).
Thus, the wiring pattern shown in FIG. 3 that may not avoid the increase in cross area involves a problem of causing an inter-layer short circuit due to dust or the like. This, in turn, may raise the detect rate of organic EL panels. In addition, the above-mentioned wiring pattern causes an increased capacity that is parasitic to the cross portion, thereby increasing the distortion of a potential waveform of the drive power supply line DSL(i).